A Nanoscaled Ground Plane Based MOSFET on Selective Buried Oxide, A Simulation Study

Sajad A. Loan*¹, Student Member, IEEE, S. Qureshi, Senior Member, IEEE, and S. Sundar Kumar Iyer, Senior member, IEEE

Electrical Engineering Department, Indian Institute of Technology Kanpur, India.

¹Electronics Engineering Department, Jamia Millia Islamia New Delhi-110025

(sajad@iitk.ac.in)

ABSTRACT

In this paper, a new nanoscaled selective buried oxide (SELBOX) based device is proposed and simulated using a 2D device simulator MEDICI. The proposed device is a nano partial ground plane (PGP) based MOSFET on SELBOX. In this device, the buried oxide is covering only source and drain regions and a nanoscaled window has been made under the channel region. The proposed device possesses the gate oxide thickness, PGP thickness and PGP length of 2 nm, 5 nm and 10 nm respectively. The self aligned nano PGP’s have been used under the SELBOX, with the edge of each PGP in line with source/drain and channel junctions. The use of heavily doped nano ground plane is an effective means to prevent the electric field lines from the drain to reach the source directly. The electric field line coupling has been minimized in the proposed device. This reduces short channel effects (SCEs), particularly drain induced barrier lowering (DIBL) in the proposed device and makes the proposed device more efficient in comparison to other device in the nanometer range. The structure retains all the advantages of the SELBOX structure and at the same time reduces SCEs significantly and makes further scaling of the device possible in nanometer regime. The schematic cross section of the three types of devices simulated in this study are shown in Fig. 1, Fig. 2 and Fig. 3. The output characteristics of these devices, as shown in Fig. 4, show that the SOI device characteristics degrades as a result of self-heating in comparison to proposed and SELBOX device. The subthreshold characteristics of the devices reveal that the subthreshold leakage current is lowest in the proposed device in comparison to other devices as shown in Fig. 5. The reason behind this is the thermal efficiency and the reduction of SCEs, particularly DIBL in the proposed device due to nano PGPs. From the potential contours for the proposed and SELBOX based device, as shown in Fig. 6 and Fig. 7 respectively, we see that there is direct coupling of electric field lines between the source and the drain region in the SELBOX device. This results in increase in DIBL in the SELBOX device. Fig. 8 and Fig. 9 shows the variation of subthreshold slope (S) and Vth with change in channel length and also DIBL As can be seen, the decrease in V_th is more in conventional SOI and SELBOX device than the proposed device. This shows that the DIBL in proposed device is less in comparison to the SELBOX based device. The subthreshold slope is better in proposed device than in the SELBOX based device. The ac simulation of the devices has been performed to extract the cutoff frequency (Ft) of the devices. It is been observed that the conventional SOI device is having best cutoff frequency than the proposed and the SELBOX device, due to less capacitance.  The cutoff frequency of the proposed device is higher than the full ground plane based device. Since the full ground planes contribute more capacitance than the nano PGPs. Table 1 shows the various device and process parameters used in the simulation of various devices studied.

Keywords: Nanodevices, Short channel effects, SOI, MOSFET, Leakage current

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*Contact author: Sajad A. Loan, Electrical Engineering Department, IIT Kanpur India

                          Phone No. +91-9919574871, +91-5122597339 Fax: +91-5122590063